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2.7 v to 5.5 v, <100 a, 14-bit nano dac, spi interface in sc70 package ad5641 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2007 analog devices, inc. all rights reserved. features 6-lead sc70 package micropower operation: 100 a maximum at 5 v power-down to typically 0.2 a at 3 v single 14-bit dac b version: 4 lsb inl a version: 16 lsb inl 2.7 v to 5.5 v power supply guaranteed monotonic by design power-on reset to 0 v with brownout detection 3 power-down functions low power serial interface with schmitt-triggered inputs on-chip output buffer amplifier, rail-to-rail operation sync interrupt facility applications voltage level setting portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators general description the ad5641, a member of the nano dac? family, is a single, 14-bit, buffered, voltage-out dac that operates from a single 2.7 v to 5.5 v supply, typically consuming 75 a at 5 v. the part comes in a tiny sc70 package. its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. the ad5641 uses a versatile 3-wire serial interface that operates at clock rates up to 30 mhz and is compatible with spi?, qspi?, microwire?, and dsp interface standards. the reference for ad5641 is derived from the power supply inputs and, therefore, gives the widest dynamic output range. the part incorporates a power-on reset circuit, which ensures that the dac output powers up to 0 v and remains there until a valid write to the device takes place. the ad5641 contains a power-down feature that reduces current consumption typically to 0.2 a at 3 v, and provides software-selectable output loads while in power-down mode. the part is put into power-down mode over the serial interface. the low power consumption of the part in normal operation makes it ideally suited to portable battery-operated equipment. the combination of small package and low power makes this nano dac device ideal for level-setting requirements such as generating bias or control voltages in space-constrained and power-sensitive applications. functional block diagram ad5641 v dd v out gnd power-on reset dac register 14-bit dac input control logic power-down control logic output buffer resistor network ref(+) sclk sdin 04611-001 sync figure 1. table 1. related devices part number description ad5601/ad5611/ad5621 2.7 v to 5.5 v, <100 a, 8-/10-/12-bit nano dac, spi interface in sc70 package product highlights 1. available in a space-saving, 6-lead sc70 package. 2. low power, single-supply operation. the ad5641 operates from a single 2.7 v to 5.5 v supply and with a maximum current consumption of 100 a, making it ideal for battery-powered applications. 3. the on-chip output buffer amplifier allows the output of the dac to swing rail-to-rail with a typical slew rate of 0.5 v/s. 4. reference derived from the power supply. 5. high speed serial interface with clock speeds up to 30 mhz. designed for very low power consumption. the interface powers up only during a write cycle. 6. power-down capability. when powered down, the dac typically consumes 0.2 a at 3 v. 7. power-on reset with brownout detection.
ad5641 rev. c | page 2 of 20 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 ter mi nolo g y .................................................................................... 12 theory of operation ...................................................................... 13 digital-to-analog section ......................................................... 13 resistor string ............................................................................. 13 output amplifier ........................................................................ 13 serial interface ............................................................................ 13 input shift register .................................................................... 13 sync interrupt .......................................................................... 13 power-on reset .......................................................................... 14 power-down modes .................................................................. 14 microprocessor interfacing ....................................................... 15 applications ..................................................................................... 16 choosing a reference as power supply for the ad5641 ...... 16 bipolar operation using the ad5641 ..................................... 16 using the ad5641 with a galvanically isolated interface .... 17 power supply bypassing and grounding ................................ 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 18 revision history 10/07rev. b to rev. c added b grade....................................................................universal changes to offset error and gain error specifications.............. 3 changes to table 4............................................................................ 5 changes to typical performance characteristics......................... 7 changes to ordering guide .......................................................... 18 7/05rev. a to rev. b change to galvanically isolated interface section..................... 18 changes to figure 44...................................................................... 18 3/05rev. 0 to rev. a changes to timing characteristics.................................................4 changes to absolute maximum ratings........................................5 changes to full-scale error section ...............................................7 changes to figures 28 and 30 ....................................................... 12 change to resistor string section................................................ 13 changes to power-down mode section ..................................... 14 1/05revision 0: initial version
ad5641 rev. c | page 3 of 20 specifications v dd = 2.7 v to 5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; ?40c < t a < +125c; typical at +25c; all specifications t min to t max , unless otherwise noted. table 2. a grade b grade parameter min typ max min typ max unit test conditions/comments static performance resolution 14 14 bits relative accuracy 1 16 4 lsb differential nonlinearity 1 1 1 lsb guaranteed monotonic by design zero-code error 0.5 10 0.5 10 mv all 0s loaded to dac register offset error 0.63 10 0.63 10 mv full-scale error 0.5 0.5 mv all 1s loaded to dac register gain error 0.004 0.037 0.004 0.037 % of fsr zero-code error drift 5.0 5.0 v/c gain temperature coefficient 2.0 2.0 ppm of fsr/c output characteristics 2 output voltage range 0 v dd 0 v dd v output voltage settling time 6 10 6 10 s code ? scale to ? scale, to 1 lsb slew rate 0.5 0.5 v/s capacitive load stability 470 470 pf r l = 1000 1000 pf rl = 2 k output noise spectral density 120 120 nv/ hz dac code = midscale, 1 khz noise 2 2 v dac code = midscale, 0.1 hz to 10 hz bandwidth digital-to-analog glitch impulse 5 5 nv-s 1 lsb change around major carry digital feedthrough 0.2 0.2 nv-s dc output impedance 0.5 0.5 short-circuit current 15 15 ma v dd = 3 v/5 v logic inputs input current 3 2 2 a v inl , input low voltage 0.8 0.8 v v dd = 4.5 v to 5.5 v 0.6 0.6 v v dd = 2.7 v to 3.6 v v inh , input high voltage 1.8 1.8 v v dd = 4.5 v to 5.5 v 1.4 1.4 v v dd = 2.7 v to 3.6 v pin capacitance 3 3 pf power requirements v dd 2.7 5.5 2.7 5.5 v all digital inputs at 0 v or v dd i dd (normal mode) dac active and excluding load current v dd = 4.5 v to 5.5 v 75 100 75 100 a v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 60 90 60 90 a v ih = v dd and v il = gnd i dd (all power-down modes) v dd = 4.5 v to 5.5 v 0.5 0.5 a v ih = v dd and v il = gnd v dd = 2.7 v to 3.6 v 0.2 0.2 a v ih = v dd and v il = gnd power efficiency i out /i dd 96 96 % i load = 2 ma and v dd = 5 v, full-scale loaded 1 linearity calculated usin g a reduced code range (c ode 256 to code 16,128). 2 guaranteed by design and characterization, not production tested. 3 total current flowing into all pins.
ad5641 rev. c | page 4 of 20 timing characteristics v dd = 2.7 v to 5.5 v; all specifications t min to t max , unless otherwise noted. see figure 2 . table 3. parameter limit 1 unit test conditions/comments t 1 2 33 ns min sclk cycle time t 2 5 ns min sclk high time t 3 5 ns min sclk low time t 4 10 ns min sync to sclk falling edge setup time t 5 5 ns min data setup time t 6 4.5 ns min data hold time t 7 0 ns min sclk falling edge to sync rising edge t 8 20 ns min minimum sync high time t 9 13 ns min sync rising edge to next sclk falling edge ignored 1 all input signals are specified with t r = t f = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 2 maximum sclk frequency is 30 mhz. t 4 t 3 t 2 t 5 t 7 t 6 d0 d1 d2 d14 d15 sync sclk 04611-002 t 9 t 1 t 8 d15 d14 sdin figure 2. timing diagram
ad5641 rev. c | page 5 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter rating v dd to gnd ?0.3 v to +7.0 v digital input voltage to gnd C0.3 v to v dd + 0.3 v v out to gnd C0.3 v to v dd + 0.3 v operating temperature range industrial C40c to +125c storage temperature range C65c to +160c maximum junction temperature 150c sc70 package ja thermal impedance 433.34c/w jc thermal impedance 149.47c/w reflow soldering peak temperature 260c time at peak temperature 20 sec to 40 sec esd 2.0 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad5641 rev. c | page 6 of 20 pin configuration and fu nction descriptions ad5641 top view (not to scale) v out sync 16 gnd sclk 25 sdin v dd 34 04611-003 figure 3. 6-lead sc70 pin configuration table 5. pin function descriptions pin no. mnemonic description 1 sync level-triggered control input (active low). this is the frame synchronization signal for the input data. when sync goes low, it enables the input shift regi ster and data is transferred in on the falling edges of the clocks that follow. the dac is updated following the 16 th clock cycle unless sync is taken high before this edge, in which case the rising edge of sync acts as an interrupt and the write sequence is ignored by the dac. 2 sclk serial clock input. data is clocked into the input shift register on the falling ed ge of the serial clock input. data can be transferred at rates up to 30 mhz. 3 sdin serial data input. this device has a 16-bit shift register. da ta is clocked into the register on the falling edge of the serial clock input. 4 v dd power supply input. the ad5641 can be operated from 2.7 v to 5.5 v. v dd should be decoupled to gnd. 5 gnd ground reference point for all circuitry on the ad5641. 6 v out analog output voltage from the dac. the o utput amplifier has rail-to-rail operation.
ad5641 rev. c | page 7 of 20 typical performance characteristics ?4 ?3 ?2 ?1 0 1 2 3 4 256 2256 4256 6256 8256 10256 12256 14256 dac code inl error (lsb) v dd = v ref = 5v t a = 25c 04611-004 figure 4. typical inl ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) inl error (lsb) max inl @ v dd = v ref = 5v max inl @ v dd = v ref = 3v min inl @ v dd = v ref = 5v min inl @ v dd = v ref = 3v 04611-005 figure 5. inl error vs. temperature (3 v/5 v supply) ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 2.73.23.74.24.7 5.2 inl error (lsb) t a = 25c supply (v) 04611-006 max inl error min inl error figure 6. inl error vs. supply at 25c ?8 ?6 ?4 ?2 0 2 4 6 8 256 2256 4256 6256 8256 10256 12256 14256 dac code tue error (lsb) c v dd = v ref = 5v t a = 25c 04611-007 figure 7. typical total unadjusted error (tue) ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) tue erro r (lsb) max tue error @ v dd = v ref = 5v min tue error @ v dd = v ref = 3v min tue error @ v dd = v ref = 5v max tue error @ v dd = v ref = 3v 04611-008 figure 8. total unadjusted error (tue) vs. temperature (3 v/5 v supply) ?15 ?10 ?5 0 5 10 2.7 3.2 3.7 4.2 4.7 5.2 supply (v) tue error (lsb) t a = 25c 04611-009 max tue error min tue error figure 9. total unadjusted error (tue) vs. supply at 25c
ad5641 rev. c | page 8 of 20 ?0.0025 ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 0.0020 0.0025 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) error (v) zero-code error @ v dd = 5v full-scale error @ v dd = 5v full-scale error @ v dd = 3v zero-code error @ v dd = 3v 04611-010 figure 10. zero-code/full-scale error vs. temperature (3 v/5 v) ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 0.0020 2.7 3.2 3.7 4.2 4.7 5.2 supply (v) error (v) t a = 25c full-scale error zero-code error 04611-011 figure 11. zero-code/full-scale error vs. supply at 25c ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 256 2256 4256 6256 8256 10256 12256 14256 dac code dnl error (lsb) v dd = 5v t a = 25c 04611-012 figure 12. typical dnl ?0.4 ?0.3 ?0.2 ?0.1 0.1 0.2 0.3 0.4 0.5 0.6 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) dnl error (lsb) 0 max dnl @ v dd = 5v min dnl @ v dd = 5v max dnl @ v dd = 3v min dnl @ v dd = 3v 04611-013 figure 13. dnl error vs. temperature (3 v/5 v) ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 2.7 3.2 3.7 4.2 4.7 5.2 supply (v) dnl error (lsb) t a = 25c 04611-014 max dnl error min dnl error figure 14. dnl error vs. supply at 25c 0 2 4 6 8 10 12 0.05456 0.05527 0.05599 0.05671 0.05742 0.05814 0.05885 0.06648 0.06710 0.06773 0.06835 0.06897 0.06960 0.07022 0.07084 0.07147 0.07209 0.07271 0.07334 i dd (ma) number of devices 04611-015 v dd = 5v v ih = dv dd v il = gnd t a = 25c v dd = 3v v ih = dv dd v il = gnd t a = 25c figure 15. i dd histogram (3 v/5 v)
ad5641 rev. c | page 9 of 20 ?1.6 ?1.5 ?1.4 ?1.3 ?1.2 ?1.1 ?1.0 ?0.9 ?0.8 ?0.7 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) offset error (mv) 04611-016 v dd = v ref = 5v v dd = v ref = 3v figure 16. offset error vs. temperature (3 v/5 v supply) ?0.016 ?0.014 ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) gain error (%fsr) v dd = 3v v dd = 5v 04611-017 figure 17. gain error vs. temperature (3 v/5 v) 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 ?40 ?20 0 20 40 60 80 100 120 140 temperature (c) i dd (ma) v dd = 3v v dd = 5v 04611-018 figure 18. supply current vs. temperature (3 v/5 v supply) 0 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 2.7 3.2 3.7 4.2 4.7 5.2 supply voltage (v) i dd (ma) t a = 25c 0.01 04611-019 figure 19. supply current vs. supply voltage at 25c ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 ?15 ?10 ?5 0 5 10 15 i (ma) v out (v) 04611-020 dac loaded with zero-scale code v dd = 5v t a = 25c dac loaded with full-scale code figure 20. sink and source capability 0 10 20 30 40 50 60 70 0 2000 4000 6000 8000 10000 12000 14000 16000 digital input code i dd (a) v dd = 5v v dd = 3v 04611-021 figure 21. supply current vs. digital input code
ad5641 rev. c | page 10 of 20 ch1 = 5v/div ch2 = 1v/div time base = 2 s/div ch1 = sclk ch2 = v out 04611-022 t a = 25c v dd = 5v figure 22. full-scale settling time ch1 = 5v/div ch2 = 1v/div time base = 2 s/div ch1 = sclk ch2 = v out t a = 25c v dd = 5v 04611-023 figure 23. midscale settling time ch2 ch1 04611-024 v dd = 5v t a = 25 c v dd v out = 70mv ch1 1v, ch2 20mv, time base = 20 s/div figure 24. power-on reset to 0 v ch1 1v, ch2 5v, time base = 50 s/div ch2 ch1 04611-025 v dd v out v dd = 5v t a = 25 c figure 25. v dd vs. v out sample number amplitude (v) 0 100 200 300 400 500 2.458 2.456 2.454 2.452 2.450 2.448 2.446 2.444 2.442 2.440 2.438 2.436 t a = 25c v dd = 5v load = 2k and 220pf code 0x2000 to 0x1fff 10ns/sample number 04611-026 figure 26. digital-to-analog glitch energy 04611-027 ch1 v dd = 5v t a = 25 c midscale loaded ch1 5 v/div figure 27. 1/f noise, 0.1 hz to 10 hz bandwidth
ad5641 rev. c | page 11 of 20 ch1 5v, ch2 1v, time base = 2s/div ch1 ch2 04611-028 v dd = 5v t a = 25c v out figure 28. exiting power-down mode 0 20 40 60 80 100 120 140 0 5 10 15 20 25 frequency (mhz) i dd ( a) 04611-029 3/4 scale full scale 1/4 scale midscale zero scale figure 29. i dd vs. sclk vs. code 04611-030 0 100 200 300 400 500 600 700 100 1000 10000 100000 frequency (hz) output noise spectral density (nv/ hz) full scale zero scale v dd = 5v t a = 25c unloaded output midscale figure 30. noise spectral density 0 50 100 150 200 250 300 350 400 450 0 v logic (v) i dd ( a) sclk/sdin increasing v dd = 3v sclk/sdin decreasing v dd = 3v sclk/sdin decreasing v dd = 5v sclk/sdin increasing v dd = 5v 6 45 3 2 1 t a = 25c 04611-044 figure 31. sclk/sdin vs. logic voltage
ad5641 rev. c | page 12 of 20 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. see figure 4 for a plot of typical inl vs. code. differential nonlinearity (dnl) differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. see figure 12 for a plot of typical dnl vs. code. zero-code error zero-code error is a measure of the output error when zero code (0x0000) is loaded to the dac register. ideally, the output should be 0 v. the zero-code error is always positive in the ad5641 because the output of the dac cannot go below 0 v. zero-code error is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in mv. see figure 10 for a plot of zero-code error vs. temperature. full-scale error full-scale error is a measure of the output error when full-scale code (0xffff) is loaded to the dac register. ideally, the output should be v dd ? 1 lsb. full-scale error is expressed in mv. see figure 10 for a plot of full-scale error vs. temperature. gain error gain error is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from ideal, expressed as a percent of the full-scale range. tot a l un a dju s te d e r ror ( t u e ) total unadjusted error is a measure of the output error taking the various errors into account. see figure 7 for a plot of typical tue vs. code. zero-code error drift zero-code error drift is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift gain error drift is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital input code is changed by 1 lsb at the major carry transition (0x2000 to 0x1fff). see figure 26 . digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac, but is measured when the dac output is not updated. it is specified in nv-s and is measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa.
ad5641 rev. c | page 13 of 20 theory of operation digital-to-analog section the ad5641 dac is fabricated on a cmos process. the architecture consists of a string dac followed by an output buffer amplifier. figure 32 is a block diagram of the dac architecture. v dd v out gnd resistor network ref (+) ref (?) [ output amplifier dac register 04611-031 figure 32. dac architecture because the input coding to the dac is straight binary, the ideal output voltage is given by u 384,16 d vv dd out where d is the decimal equivalent of the binary code that is loaded to the dac register; it can range from 0 to 16,384. resistor string the resistor string structure is shown in figure 33 . it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaran- teed monotonic. r r r r r to output amplifier 04611-032 figure 33. resistor string structure output amplifier the output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0 v to v dd . it is capable of driving a load of 2 k in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 20 . the slew rate is 0.5 v/s, with a midscale settling time of 8 s with the output loaded. serial interface the ad5641 has a 3-wire serial interface ( sync , sclk, and sdin) that is compatible with spi, qspi, and microwire interface standards, as well as most dsps. see figure 2 for a timing diagram of a typical write sequence. the write sequence begins by bringing the sync line low. data from the sdin line is clocked into the 16-bit shift register on the falling edge of sclk. the serial clock frequency can be as high as 30 mhz, making the ad5641 compatible with high speed dsps. on the 16 th falling clock edge, the last data bit is clocked in and the programmed function is executed (a change in dac register contents and/or a change in the mode of operation). at this stage, the sync line can be kept low or brought high. in either case, it must be brought high for a minimum of 20 ns before the next write sequence, so that a falling edge of sync can initiate the next write sequence. because the sync buffer draws more current when v in = 1.8 v than it does when v in = 0.8 v, sync should be idled low between write sequences for even lower power operation of the part, as previously mentioned. however, it must be brought high again just before the next write sequence. input shift register the input shift register is 16 bits wide (see figure 34 ). the first two bits are control bits, which determine the operating mode of the part (normal mode or any one of three power-down modes). for a complete description of the various modes, see the power- down modes section. the next 14 bits are the data bits, which are transferred to the dac register on the 16 th falling edge of sclk. sync interrupt in a normal write sequence, the sync line is kept low for at least 16 falling edges of sclk and the dac is updated on the 16 th falling edge. however, if sync is brought high before the 16 th falling edge, this acts as an interrupt to the write sequence. the shift register is reset and the write sequence is seen as invalid. neither an update of the dac register contents nor a change in the operating mode occurs (see figure 35 ).
ad5641 rev. c | page 14 of 20 data bits db15 (msb) db0 (lsb) pd1 pd0 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 normal operation 1 k to gnd 100 k to gnd three-state power-down modes 0 0 1 1 0 1 0 1 04611-033 figure 34. input register contents 04611-034 db15 db16 db0 db0 invalid write sequence: sync high before 16 th falling edge valid write sequence, output updates on the 16 th falling edge sync sclk sdin figure 35. sync interrupt facility power-on reset the ad5641 contains a power-on reset circuit that controls the output voltage during power-up. the dac register is filled with 0s and the output voltage is 0 v. it remains there until a valid write sequence is made to the dac. this is useful in applica- tions in which it is important to know the state of the dac output while it is in the process of powering up. power-down modes the ad5641 has four separate modes of operation. these modes are software programmable by setting two bits (db15 and db14) in the control register. tabl e 6 shows how the state of the bits corresponds to the operating mode of the device. table 6. operating modes for the ad5641 db15 db14 operating mode 0 0 normal operation power-down mode: 0 1 1 k to gnd 1 0 100 k to gnd 1 1 three-state when both bits are set to 0, the part has normal power consumption of 100 a maximum at 5 v. however, for the three power-down modes, the supply current falls to typically 0.2 a at 3 v. not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has the advantage that the output impedance of the part is known while the part is in power-down mode. there are three different options: the output is connected internally to gnd through either a 1 k resistor or a 100 k resistor, or the output is left open-circuited (three-stated). figure 36 shows the output stage. power-down circuitry resistor network v out resistor string dac amplifier 04611-035 figure 36. output stage during power-down the bias generator, output amplifier, resistor string, and other associated linear circuitry are all shut down when power-down mode is activated. however, the contents of the dac register are unaffected when in power-down. the time to exit power- down is typically 13 s for v dd = 5 v and 16 s for v dd = 3 v. see figure 28 for a plot.
ad5641 rev. c | page 15 of 20 microprocessor interfacing ad5641 to adsp-2101 interface figure 37 shows a serial interface between the ad5641 and the adsp-2101 . the adsp-2101 should be set up to operate in sport transmit alternate framing mode. the adsp-2101 sport is programmed through the sport control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. transmission is initiated by writing a word to the tx register after the sport is enabled. ad5641* *additional pins omitted for clarity tfs dt sclk sync sdin sclk 04611-036 adsp-2101* figure 37. ad5641 to adsp-2101 interface ad5641 to 68hc11/68l11 interface figure 38 shows a serial interface between the ad5641 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5641, while the mosi output drives the serial data line of the dac. the sync signal is derived from a port line (pc7). the setup conditions for correct operation of this interface are as follows: the 68hc11/68l11 should be configured so that the cpol bit is 0 and the cpha bit is 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 are config- ured as previously described, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb first. to load data to the ad5641, pc7 is left low after the first eight bits are transferred and a second serial write operation is performed to the dac. pc7 is taken high at the end of this procedure. ad5641* *additional pins omitted for clarity pc7 sck mosi sync sclk sdin 04611-037 68hc11/ 68l11* figure 38. ad5641 to 68hc11/68l11 interface ad5641 to blackfin? adsp-bf53x interface figure 39 shows a serial interface between the ad5641 and the blackfin adsp-bf53x microprocessor. the adsp-bf53x processor family incorporates two dual-channel synchronous serial ports, sport1 and sport0, for serial and multi- processor communications. using sport0 to connect to the ad5641, the setup for the interface is as follows: dt0pri drives the sdin pin of the ad5641, while tsclk0 drives the sclk of the part. the sync is driven from tfs0. adsp-bf53x* ad5641* *additional pins omitted for clarity dt0pri tsclk0 tfs0 sdin sclk sync 04611-038 figure 39. ad5641 to blackfin adsp-bf53x interface ad5641 to 80c51/80l51 interface figure 40 shows a serial interface between the ad5641 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the ad5641, while rxd drives the serial data line of the part. the sync signal is again derived from a bit-programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmitted to the ad5641, p3.3 is taken low. the 80c51/80l51 transmits data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/80l51 outputs the serial data lsb first. the ad5641 requires its data with the msb as the first bit received. the 80c51/80l51 transmit routine should take this into account. 80c51/80l51* ad5641* *additional pins omitted for clarity p3.3 txd rxd sync sclk sdin 04611-039 figure 40. ad5641 to 80c51/80l51 interface ad5641 to microwire interface figure 41 shows an interface between the ad5641 and any microwire-compatible device. serial data is shifted out on the falling edge of the serial clock and is clocked into the ad5641 on the rising edge of sk. microwire* ad5641* *additional pins omitted for clarity cs sk so sync sclk sdin 04611-040 figure 41. ad5641 to microwire interface
ad5641 rev. c | page 16 of 20 applications choosing a reference as power supply for the ad5641 the ad5641 comes in a tiny sc 70 package with less than 100 a supply current. because of this, the choice of reference depends on the application requirement. for space-saving applications, the adr02 is available in an sc70 package and has excellent drift at 9 ppm/c (3 ppm/c in the r-8 package). it also provides very good noise performance at 3.4 v p-p in the 0.1 hz to 10 hz range. because the supply current required by the ad5641 is extremely low, the parts are ideal for low supply applications. the adr395 voltage reference is recommended in this case. it requires less than 100 a of quiescent current and can, therefore, drive multiple dacs in one system, if required. it also provides very good noise performance at 8 v p-p in the 0.1 hz to 10 hz range. ad 5641 3-wire serial interface sync sclk sdin 7v 5v v out = 0v to 5v adr395 04611-041 figure 42. adr395 as power supply to ad5641 table 7 lists some recommended precision references for use as supplies to the ad5641. table 7. precision references for use with ad5641 part no. initial accuracy (mv max) temperature drift (ppm/c max) 0.1 hz to 10 hz noise (v p-p typ) adr435 2 3 (r-8) 8 adr425 2 3 (r-8) 3.4 adr02 3 3 (r-8) 10 adr02 3 3 (sc70) 10 adr395 5 9 (tsot-23) 8 bipolar operation using the ad5641 the ad5641 has been designed for single-supply operation, but a bipolar output range is also possible using the circuit in figure 43 . the circuit in figure 43 gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or op295 as the output amplifier. r2 = 10k 04611-042 +5v ?5v ad820/ op295 3-wire serial interface +5v ad5641 10 f 0.1 f v dd v out r1 = 10k +5v figure 43. bipolar operation with the ad5641 the output voltage for any input code can be calculated as ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = r1 r2 v r1 r2r1d vv dd dd out 384,16 where d represents the input code in decimal (0 C 16384). with v dd = 5 v, r1 = r2 = 10 k, v5 384,16 10 ? ? ? ? ? ? ? ? ? = d v out this is an output voltage range of 5 v with 0x0000 corre- sponding to a C5 v output, and 0x3fff corresponding to a +5 v output.
ad5641 rev. c | page 17 of 20 using the ad5641 with a galvanically isolated interface in process control applications in industrial environments, it is often necessary to use a galvanically isolated interface to protect and isolate the controlling circuitry from any hazardous common-mode voltages that might occur in the area where the dac is functioning. i coupler? provides isolation in excess of 2.5 kv. the ad5641 use a 3-wire serial logic interface, so the adum1300 three-channel digital isolator provides the required isolation (see figure 44 ). the power supply to the part also needs to be isolated, which is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5641. v dd ad5641 adum1300 power 10f 0.1f gnd 5v regulator sclk voa v out vob sync voc via vib vic sclk sdi data sdin 04611-043 figure 44. ad5641 with a galvanically isolated interface power supply bypassing and grounding when accuracy is important in a circuit, it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5641 should have separate analog and digital sections, each having its own area of the board. if the ad5641 is in a system where other devices require an agnd-to-dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5641. the power supply to the ad5641 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be physically as close as possible to the device, with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and effective series inductance (esi), such as in common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high frequencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals, if possible. when traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects on the board. the best board layout technique is the microstrip technique, where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the so lder side. however, this is not always possible with a 2-layer board.
ad5641 rev. c | page 18 of 20 outline dimensions compliant to jedec standards mo-203-ab 0.22 0.08 0.30 0.10 0.30 0.15 1.00 0.90 0.70 seating plane 4 5 6 3 2 1 pin 1 0.65 bsc 1.30 bsc 0.10 max 0.10 coplanarity 0.40 0.10 1.10 0.80 2.20 2.00 1.80 2.40 2.10 1.80 1.35 1.25 1.15 figure 45. 6-lead thin shrink small outline transistor package [sc70] (ks-6) dimensions shown in millimeters ordering guide model temperature range description package description package option branding ad5641aksz-reel7 1 C40c to +125c 16 lsb inl 6-lead thin shrink small outline transistor package [sc70] ks-6 d3q ad5641aksz-500rl7 1 C40c to +125c 16 lsb inl 6-lead thin shrink small outline transistor package [sc70] ks-6 d3q ad5641bksz-reel7 1 C40c to +125c 4 lsb inl 6-lead thin shrink small outline transistor package [sc70] ks-6 d3p AD5641BKSZ-500RL7 1 C40c to +125c 4 lsb inl 6-lead thin shrink small outline transistor package [sc70] ks-6 d3p 1 z = rohs compliant part.
ad5641 rev. c | page 19 of 20 notes
ad5641 rev. c | page 20 of 20 notes ?2005C2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d04611-0-10/07(c)

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